Thursday, 15 November 2012

Net Delay or Interconnect Delay or Wire Delay or Extrinsic Delay or Flight Time

Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.
It is due to the finite resistance and capacitance of the net. It is also known as wire delay.
Wire delay = function of (Rnet, Cnet+Cpin)

2 comments:

  1. Love this valuable information, especially CMOS history. I was searching about CMOS and SiGe technologies to check a fact came online and ended up here, instead going further I read your post and it is helpful. Thanks for sharing your knowledge. Asic Chip Design and supply

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